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FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 1 january 2013 FDMS3669S powertrench ? power stage asymmetric dual n-channel mosfet features q1: n-channel ? max r ds(on) = 10 m at v gs = 10 v, i d = 13 a ? max r ds(on) = 14.5 m at v gs = 4.5 v, i d = 10 a q2: n-channel ? max r ds(on) = 5 m at v gs = 10 v, i d = 18 a ? max r ds(on) = 5.2 m at v gs = 4.5 v, i d = 17 a ? low inductance packaging shortens rise/fall times, resulting in lower switching losses ? mosfet integration enables optimum layout for lower circuit inductance and reduced switch node ringing ? rohs compliant general description this device includes two specia lized n-channel mosfets in a dual pqfn package. the switch node has been internally connected to enable easy placement and routing of synchronous buck converters. the contro l mosfet (q1) and synchronous syncfet tm (q2) have been designed to provide optimal power efficiency. applications ? computing ? communications ? general purpose point of load ? notebook vcore mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 30 30 v v gs gate to source voltage (note 3) 20 12 v i d drain current -continuous (package limited) t c = 25 c 24 60 a -continuous (silicon limited) t c = 25 c 43 75 -continuous t a = 25 c 13 1a 18 1b -pulsed (note 6) 50 60 e as single pulse avalanche energy 61 4 48 5 mj p d power dissipation for single operation t a = 25 c 2.2 1a 2.5 1b w power dissipation for single operation t a = 25 c 1.0 1c 1.0 1d t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient 57 1a 50 1b c/w r ja thermal resistance, junction to ambient 125 1c 120 1d r jc thermal resistance, junction to case 5.0 2.8 device marking device package reel size tape width quantity 9acf 21cd FDMS3669S power 56 13 ? 12 mm 3000 units 4 3 2 1 5 6 7 8 q 1 q 2 power 56 g1 d1 d1 d1 g2 s2 s2 s2 d1 phase (s1/d2) s2 s2 s2 g2 d1 d1 d1 g1 top bottom phase pin 1 pin 1
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 2 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics symbol parameter test conditions type min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v i d = 1 ma, v gs = 0 v q1 q2 30 30 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 10 ma, referenced to 25 c q1 q2 16 20 mv/c i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v q1 q2 1 500 a a i gss gate to source leakage current v gs = 20 v, v ds = 0 v v gs = 12 v, v ds = 0 v q1 q2 100 100 na na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a v gs = v ds , i d = 1 ma q1 q2 1.1 1.1 2.0 1.5 2.7 2.5 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 10 ma, referenced to 25 c q1 q2 -6 -3 mv/c r ds(on) drain to source on resistance v gs = 10 v, i d = 13 a v gs = 4.5 v, i d = 10 a v gs = 10 v, i d = 13 a , t j = 125 c q1 8.1 12 11 10 14.5 14.5 m v gs = 10 v, i d = 18 a v gs = 4.5 v, i d = 17 a v gs = 10 v, i d = 18 a , t j = 125 c q2 2.8 3.5 4.0 5.0 5.2 7.1 g fs forward transconductance v ds = 5 v, i d = 13 a v ds = 5 v, i d = 18 a q1 q2 53 113 s c iss input capacitance q1: v ds = 15 v, v gs = 0 v, f = 1 mhz q2: v ds = 15 v, v gs = 0 v, f = 1 mhz q1 q2 1205 1469 1605 2060 pf c oss output capacitance q1 q2 370 485 495 680 pf c rss reverse transfer capacitance q1 q2 35 59 55 90 pf r g gate resistance q1 q2 0.3 0.2 1.6 1.4 3.2 3.0 t d(on) turn-on delay time q1: v dd = 15 v, i d = 13 a, r gen = 6 q2: v dd = 15 v, i d = 18 a, r gen = 6 q1 q2 9 7 18 14 ns t r rise time q1 q2 3 3 10 10 ns t d(off) turn-off delay time q1 q2 20 24 36 40 ns t f fall time q1 q2 3 3 10 10 ns q g total gate charge v gs = 0 v to 10 v q1: v dd = 15 v, i d = 13 a q2: v dd = 15 v, i d = 18 a q1 q2 17 24 24 34 nc q g total gate charge v gs = 0 v to 4.5 v q1 q2 7.5 12 12 17 nc q gs gate to source gate charge q1 q2 3.9 3.3 nc q gd gate to drain ?miller? charge q1 q2 2.0 3.6 nc
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 3 electrical characteristics t j = 25 c unless otherwise noted drain-source diod e characteristics symbol parameter test conditions type min typ max units v sd source to drain diode forward voltage v gs = 0 v, i s = 13 a (note 2) v gs = 0 v, i s = 2 a (note 2) v gs = 0 v, i s = 18 a (note 2) v gs = 0 v, i s = 2 a (note 2) q1 q1 q2 q2 0.8 0.7 0.8 0.7 1.2 1.2 1.2 1.2 v t rr reverse recovery time q1: i f = 13 a, di/dt = 100 a/ s q2: i f = 18 a, di/dt = 300 a/ s q1 q2 24 21 38 33 ns q rr reverse recovery charge q1 q2 8 16 15 31 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. as an n-ch device, the negative vgs rating is for low duty cycle pulse ocurrence only. no continuous rating is implied with the negative vgs rating. 4. e as of 61 mj is based on starting t j = 25 o c; n-ch: l = 3 mh, i as = 6.4 a, v dd = 30 v, v gs = 10 v. 100% test at l= 0.1 mh, i as = 20 a. 5. e as of 48 mj is based on starting t j = 25 o c; n-ch: l = 3 mh, i as = 5.7 a, v dd = 30 v, v gs = 10 v. 100% test at l= 0.1 mh, i as = 17 a. 6. pulsed id limited by junction temperature,td<=10us. please refer to soa curve for more details. a. 57 c/w when mounted on a 1 in 2 pad of 2 oz copper c. 125 c/w when mounted on a minimum pad of 2 oz copper b. 50 c/w when mounted on a 1 in 2 pad of 2 oz copper d. 120 c/w when mounted on a minimum pad of 2 oz copper g df ds sf ss g df ds sf ss g df ds sf ss g df ds sf ss
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 4 typical characteristics (q1 n-channel) t j = 25 c unless otherwise noted figure 1. 0.0 0.5 1.0 1.5 2.0 2.5 0 10 20 30 40 50 v gs = 6 v v gs = 10 v v gs = 4.5 v v gs = 4 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max i d , drain current (a) v ds , drain to source voltage (v) on region characteristics f i g u r e 2 . 0 1020304050 0 1 2 3 4 5 v gs = 4.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 6 v v gs = 3.5 v v gs = 4 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 13 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 5 10 15 20 25 30 t j = 125 o c i d = 13 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 12345 0 10 20 30 40 50 t j = 25 o c t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.1 1 10 50 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 5 figure 7. 0 3 6 9 12 15 18 0 2 4 6 8 10 i d = 13 a v dd = 10 v v dd =15 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 20 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 1000 2000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 10 40 1 5 10 15 20 25 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 10 20 30 40 50 limited by package v gs = 4.5 v r t jc = 5.0 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) maximum continuous drain current vs case temperature fi g ure 11 . fo rw ard bi as safe op erating area f i g u r e 1 2 . s i n g l e p u l s e m a x i m u m power dissipa tion typical characteristics (q1 n-channel) t j = 25 c unless otherwise noted 0.01 0.1 1 10 100200 0.01 0.1 1 10 100 100 p s dc 100 ms 10 ms 1 ms 1 s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds ( on ) single pulse t j = max rated r t ja = 125 o c/w t a = 25 o c 10 s 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.1 1 10 100 1000 single pulse r t ja = 125 o c/w p ( pk ) , peak transient power (w) t, pulse width (sec)
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 6 figure 13. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 2 single pulse r t ja = 125 o c/w (note 1c) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics (q1 n-channel) t j = 25 c unless otherwise noted
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 7 typical characteristics (q2 n-channel) t j = 25 o c unlenss otherwise noted 0.0 0.3 0.6 0.9 1.2 1.5 0 15 30 45 60 v gs = 2.5 v v gs = 3 v v gs = 10 v v gs = 4.5 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max i d , drain current (a) v ds , drain to source voltage (v) figure 14. on-region characteristics 0 15304560 0 2 4 6 8 v gs = 3 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 2.5 v v gs = 4.5 v v gs = 10 v figure 15. normalized on-resistance vs drain current and gate voltage figure 16. normalized on-resistance vs junction temperature -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 18 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 24681 0 0 5 10 15 20 t j = 125 o c i d = 18 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max figure 17. on-resistance vs gate to source voltage figure 18. transfer characteristics 1.0 1.5 2.0 2.5 3.0 0 15 30 45 60 t j = 125 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 19. source to drain diode forward voltage vs source current 0.0 0.2 0.4 0.6 0.8 1.0 1e-3 0.01 0.1 1 10 100 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
typical characteristics (q2 n-channel) t j = 25 o c unless otherwise noted figure 20. gate ch arge characteristics 01 02 03 0 0 2 4 6 8 10 i d = 17 a v dd = 20 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 15 v 0.1 1 10 30 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss figure 21. capacitance vs drain to source voltage figure 22. unclamped inductive swit ching capability 1e-3 0.01 0.1 1 10 100 1 10 100 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) 25 50 75 100 125 150 0 20 40 60 80 limited by package r t jc = 2.8 o c/w v gs = 4.5 v v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) figure 23. maximun continuous drain current vs case temperature f i g u r e 2 4 . f o r w a r d b i a s s a f e op erating area figure 25. single pulse maximum po wer dissipation FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 8 0.01 0.1 1 10 100200 0.01 0.1 1 10 100 curve bent on measured data 100 p s dc 100 ms 10 ms 1 ms 1s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds ( on ) single pulse t j = max rated r t ja = 120 o c/w t a = 25 o c 10s 10 -4 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.5 1 10 100 1000 2000 single pulse r t ja = 120 o c/w p ( pk ) , peak transient power (w) t, pulse width (sec)
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 9 typical characteristics (q2 n-channel) t j = 25 o c unless otherwise noted figure 26. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 10 0 10 1 100 1000 1e-4 1e-3 0.01 0.1 1 2 single pulse r ja = 120 o c/w (note 1d) duty cycle-descending order normalized thermal impedance, z ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 10 syncfet tm schottky body diode characteristics fairchild?s syncfet tm process embeds a schottky diode in parallel with powertrench mosfet . this diode exhibits similar characteristics to a discrete exte rnal schottky diode in parallel with a mosfet. figure 27 shows the reverse recovery characteristic of the FDMS3669S. schottky barrier diodes exhibit significant leakage at high tem- perature and high reverse voltage. this will increase the power in the device. -40 0 40 80 120 160 -5 0 5 10 15 20 didt = 300 a/ s current (a) time (ns) typical char acteristics (continued) figure 27. FDMS3669S syncfet tm body diode reverse recovery characteristic figure 28. syncfet tm body diode reverse leakage versus drain-source voltage 0 5 10 15 20 25 30 10 -6 10 -5 10 -4 10 -3 10 -2 t j = 125 o c t j = 100 o c t j = 25 o c i dss , reverse leakage current (a) v ds , reverse voltage (v)
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 11 application information 1. switch node ringing suppression fairchild?s power stage products incorporate a proprietary desi gn* that minimizes the peak overshoot, ringing voltage on the sw itch node (phase) without the need of any external snubbing components in a buck converter. as shown in the figure 29, the power sta ge solution rings significantly less than competitor solutions under the same set of test conditions. power stage device competitors solution figure 29. power stage phase node rising edge, high side turn on *patent pending
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 12 figure 30. shows the power stage in a buck converter topology 2. recommended pcb layout guidelines as a pcb designer, it is necessary to addres s critical issues in layout to minimize losses and optimize the performance of the power train. power stage is a high power density solution and all high current flow paths, such as vin (d1), phase (s1/d2) and gnd (s 2), should be short and wide for better and stable current flow, heat radiation and system performance. a recommended layout proce- dure is discussed below to maximize the elec trical and thermal performance of the part. figure 31. recommended pcb layout
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 13 following is a guideline, not a requirement which the pcb designer should consider: 1. input ceramic bypass capacitors c1 and c2 must be placed close to the d1 and s2 pins of power stage to help reduce parasiti c inductance and high frequency conduction loss induced by switching operation. c1 and c2 show the bypass capacitors placed close to the part between d1 and s2. input capacitors should be connec ted in parallel close to the part. multiple input caps can be connected depending upon the application. 2. the phase copper trace serves two purpos es; in addition to being the current path from the power stage package to the output inductor (l), it also serves as heat sink for the lower fe t in the power stage package. the trace should be short and wide enou gh to present a low resistance path for the high current flow between t he power stage and the inductor. this is done to minimize cond uction losses and limit temperature rise. please note that the phase node is a high voltage and high frequency switching node with hig h noise potential. care should be taken to mi nimize coupling to adjacent traces. the reference layout in figure 31 shows a good b alance between the thermal and electrical performance of power stage. 3. output inductor location should be as cl ose as possible to the power stage device fo r lower power loss due to copper trace resistance. a shorter and wider phase trace to the inductor r educes the conduction loss. preferably the power stage should be directly in line (as shown in figure 31) with the inductor for space savings and compactness. 4. the powertrench ? technology mosfets used in the power stage are effe ctive at minimizing phase node ringing. it allows the part to operate well within the breakdown voltage limits. this e liminates the need to have an exter nal snubber circuit in most cases. if the designer chooses to use an rc snubber, it should be placed close to the part between the phase pad and s2 pins to dampen the high-frequency ringing. 5. the driver ic should be placed close to the power stage part with the shortest possible paths for the high side gate and low side gates through a wide trace connection. this eliminates the e ffect of parasitic inductance and resistance between the driver and the mosfet and turns the devices on and off as efficiently as possible. at higher-fre quency operation this impedance can limit the gate current trying to charge the mosfet input capacitance. this will result in slower rise and fall times and additional switching losses. power stage has both the gate pins on the same side of the pack age which allows for back mounting of the driver ic to the board . this provides a very compact path for the drive signals and improves efficiency of the part. 6. s2 pins should be connected to the gnd plane with multiple vias for a low impedance grounding. poor grounding can create a n oise transient offset voltage level between s2 and driver ground. this could lead to faulty operation of the gate driver and mosfet. 7. use multiple vias on each copper area to interconnect top, i nner and bottom layers to help smooth current flow and heat cond uction. vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. critic al high frequency components suc h as ceramic bypass caps should be located close to the part and on t he same side of the pcb. if not feasible, they should be connec ted from the backside via a network of low inductance vias.
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 14 dimensional outlin e and pad layout 3.16 2.80 c l l c pkg pk g 5. 10 4.90 6. 25 5. 90 c 3. 81 1. 02 0.82 top view side view bottom view option - a (sawn type) 14 85 123 4 876 0.1 0 cab 0.0 5 c 2.25 2.05 5 0.65 0.38 detail 'a' (scale: 2x) 0. 05 0. 00 0.35 0.15 0.08 c seating plane 0.10 c 1.10 0.90 recommended land pattern 0.65 typ 1 2 3 4 5 6 7 8 1.27 1.34 1.12 a 0.10 c (2x ) b 0.10 c (2 x) 0.00 0. 00 1. 60 2. 52 1. 21 2. 31 1. 18 1.27 typ 2.00 2.15 0. 63 0. 63 0.59 3. 18 4.00 c l c l 0.65 0.38 2.13 3. 15 0.35 0.30 0.70 0.36 4.08 3. 70 0.44 0.24 (6x) 0. 66? 05 4.16 0.61 0.31 ke ep out area 8x pin # 1 in d ic ator 5.10 see detail a (8x) for sawn / punched type
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 15 dimensional outline and pad layout detail 'b' (scale: 2x) 0.35 0.15 0.28 0.08 10? notes: unless otherwise spe cified a) package standard reference: jedec registration, mo-240, variation aa. b) all dimens ions a re in mil limeters. c) dimensions do not include burrs or mold fl ash. mold flash or burrs does not exceed 0.1 0mm. d) di men si oni ng an d to leran c in g pe r asme y14.5m-1994. e) it is re commended to have no traces or vias within the keep out area. f) drawing file name: pqn08erev5. c l l c pk g pkg 5. 10 4.90 6.25 5.90 c 3. 16 2. 80 3.81 1.02 0. 82 top view side view 14 85 1234 876 0.10 cab 0.05 c 5 0. 65 0. 38 see detail b 1.27 0.66? 05 1.34 1.12 (2x) (2x) 0. 65 0. 38 0. 35 0. 30 0. 70 0. 36 4.08 3. 70 0.44 0.24 (6x) 5.00 4. 80 5.90 5.70 0.41 0.21 (8x) 2. 25 2. 05 0.61 0.31 0.10 c 1.10 0.90 0.35 0.15 se ating pl ane 8x see detail c detail 'c' (scale: 2x) bottom view option - b (punched type) (8x) 0.10 c 0.10 c 0.08 c
FDMS3669S powertrench ? power stage ?2013 fairchild semiconductor corporation FDMS3669S rev.c1 www.fairchildsemi.com 16 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions , specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fa irchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably ex pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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* serdes? uhc ? ultra frfet? unifet? vcx? visualmax? voltageplus? xs? ? ? tm datasheet identification product status definition advance information formative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the ri ght to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fair child semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product t hat is discontinued by fairchild semiconductor. the datasheet is for reference information only. anti-counterfeiting policy fairchild semiconductor corporation?s anti-counterfeiting policy. fairchild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of semiconductor parts is a growing problem in th e industry. all manufactures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts ex perience many problems such as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing de lays. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairchild strongly encourages cu stomers to purchase fairchild parts either directly from fa irchild or from authorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fairchild?s quality standards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our custom ers to do their part in stopping this practice by buying direct or from authorized distributors. rev. i61 tm ?

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